1. Field
Various embodiments of the present invention relate to semiconductor design technology, and more particularly, to a power-up signal generation circuit in a semiconductor device.
2. Description of the Related Art
Semiconductor devices, such as a dynamic random access memory (DRAM), generally include a power-up signal generation circuit to secure a stable operation of an internal circuit. When an external power voltage VDD is supplied to a semiconductor device, the external power voltage VDD gradually increases to a target level.
However, if the external power voltage VDD is directly supplied to the internal circuit of the semiconductor device before the external power voltage VDD reaches the target level a latch-up phenomenon may occur. Thus, the semiconductor device may be damaged. To prevent such phenomenon from occurring, a power-up signal generation circuit is included in the semiconductor device. The power-up signal generation circuit activates a power-up signal when the external power voltage VDD reaches the target level to stably operate the internal circuit and initialize the semiconductor device.
FIG. 1 is a circuit diagram illustrating a conventional power-up signal generation circuit, and FIG. 2 shows timing diagrams of an external power voltage VDD and a power-up signal PWRUP in the power-up signal generation circuit shown in FIG. 1.
Referring to FIG. 1, the external power voltage VDD supplied to the power-up signal generation circuit is divided by resistors R11 and R12, and the divided voltage is outputted as a level tracing voltage V_LEVEL. The level tracing voltage V_LEVEL has a voltage level that linearly varies according to a level of the external power voltage VDD.
An NMOS transistor N11 receives the level tracing voltage V_LEVEL through a gate thereof and is turned on more strongly as the level of the external power voltage VDD becomes higher. As the NMOS transistor N11 is turned on more strongly, a detection voltage V_DET becomes lower gradually. When the detection voltage V_DET is lower than a certain level, that is, when the external power voltage VDD becomes higher than a target voltage V_TARGET, the power-up signal PWRUP is activated to a logic high level by an inverter.
Referring to FIG. 2, a variation of the power-up signal PWRUP based on variation of the external power voltage VDD is described herein, along with the concerns of the conventional technology for the power-up signal PWRUP.
In a duration prior to a time “t1” the external power voltage VDD, which is applied to a circuit to turn on the power of a semiconductor device, is gradually increased. However, since the external power voltage VDD has not yet reached the target voltage V_TARGET, the power-up signal PWRUP is in a deactivated state of a logic low level.
In a duration between the time “t1” and a time “t2”, the external power voltage VDD is increased higher than the target voltage V_TARGET. The NMOS transistor N11 is strongly turned on to enable the power-up signal PWRUP to a logic high level.
In a duration between the time “t2” and a time “t3”, the current consumption amount of the semiconductor device is increased and the external power voltage VDD drops. For example, such a voltage drop may occur when a DRAM device performs an active operation “ACT”. When the external power voltage VDD drops lower than the target voltage V_TARGET, the detection voltage V_DET may be raised. When the detection voltage V_DET is raised and then drops, the power-up signal PWRUP is reset “RESET” and as a result the semiconductor device in the middle of an operation may be inadvertently initialized again.